The present invention relates to a method for forming a semiconductor device, and more particularly, to a semiconductor device including a bit line provided at a lower portion of a gate and a method for forming the same.
In recent years, most electronic appliances include semiconductor devices. A semiconductor device includes electronic elements such as transistors, resistors, capacitors, and the like which are then integrated on a semiconductor substrate. The electronic elements are designed to execute partial functions of the electronic appliances. For example, electronic appliances such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling the information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
In order to satisfy memories of large quantity, excellent performance and cheap cost, there is a need for highly integrated semiconductor devices. For this reason, a design rule applied to a design of a semiconductor device inevitably decreases. Accordingly, so as to form more patterns in a limited region, a denser pattern should be formed by reducing a line width of the patterns. However, since there is a limitation in forming smaller patterns due to the limitation of the resolution, it is difficult to form the denser pattern using an exposure source. Furthermore, as a line width of a semiconductor device pattern is reduced, defects such as a short channel effect can occur to deteriorate the characteristics of a transistor.
Accordingly, there have been proposed various methods to form highly integrated semiconductor devices in a limited area. For example, a recess gate and a buried gate have been proposed instead of a planar gate used in the related art. In the recess gate a semiconductor substrate is etched to a predetermined thickness to form a recess, and a gate is then formed in an upper portion of the recess. The recess gate is advantageous in that an occupied area of a conventional horizontal channel region is reduced. In the buried gate a semiconductor substrate is etched to a predetermined thickness to form a recess, and the whole gate is then buried in the recess. An area of the buried gate is reduced in comparison with the recess gate.
Additionally, a fin type gate has a fin channel structure in which a tri gate wraps a channel. The fin channel structure can be manufactured in a three-dimensional structure without departing from conventional manufacturing technology. Since the fin channel structure has excellent gate control force due to structural properties to decrease short channel effect, it may minimize influence between a drain region and a source region. Moreover, the fin channel structure may reduce a channel doping density, thereby improving a leakage current through a junction region.
However, in the recess gate, the buried gate, and the fin type gate, the manufacturing process is complicated which increases the number of processes. This causes self align contact (SAC) defects, which leads to a reduction in reliability of a semiconductor device.
Furthermore, there has been suggested an arrangement forming a buried bit line which buries a bit line in a semiconductor substrate. However, it increases the number of masks used to form the buried bit line, thereby increasing the cost and the time.